1. Field of the Invention
The invention relates generally to methods and apparatus for rendering images for a display device, and more particularly to methods and apparatus that perform image operations based on bit length transfer (BLT) commands.
2. Description of Related Art
Graphics accelerators, also known as graphics processors, have evolved that incorporate 2D and 3D rendering engines to provide enhanced images for computers display, HDTVs, and other suitable display devices. Such rendering engines typically render images into rendering memory. The final image is then flipped into display memory or copied into display memory. As known, an application, such as a word processing program, video game, or other application, provides drawing commands to an operating system and/or a graphics processor. One type of command is called a render BLT command which is a bit, length, transfer command which essentially is a command to copy bits from one location to another, sometimes referred to as a copy command. One type of BLT command is a full screen BLT command which requires a full screen of bits to be copied into system memory, into a frame buffer, or any other suitable location to, for example, free up rendering memory. Accordingly, a BLT command requires, for example, a graphics processor to copy pixels from one memory block to another memory block. A full screen BLT operation is time consuming since it requires movement of all of the pixel values from one location to another location. Conventional graphics processors will use a portion of memory to render three dimensional images or two dimensional images, for example, and then the application will require the graphics processor to BLT the rendered image to a display memory in a frame buffer. The display memory is then read by a suitable display controller and the pixel values then are presented to a display device.
Another command often used by applications is a FLIP command which flips a rendered image from a back buffer to a front buffer, for example, by changing the display address that is to be used by a display controller. The front buffer is typically the actively viewed buffer. The 2D-3D rendering engine typically renders by drawing triangles and uses the back buffer to render the image after which time a FLIP command is used to change the display address used by display controller to read the back buffer as though it were the front or actively viewed buffer. Such a command is typically more efficient since it does not require the copying of pixel values from one memory block to another.
With high performance graphics drivers that are typically shipped with or downloaded for use with graphics processors, it is desirable to have the graphics drivers enhance the processing of image information to allow high performance games and other imaging devices to provide a fast and high quality display of images.
A problem arises with applications that may only use BLT commands. With graphics processors that provide a FLIP operation, performing a BLT operation can unnecessarily reduce the performance of the graphics processing device. Applications that require that an image be rendered into a back buffer and issue a BLT command, require the copying of pixels from the back buffer into the front buffer so that the active buffer is always the same buffer. This BLT operation is time consuming and potentially unnecessary and can drastically reduce the performance capabilities of a graphics processing device since the same buffer is always used as the rendering buffer.
The problem becomes increasingly burdensome when a dual graphics processor system or multi-graphics processor system is required to render under control of such applications. For example, with dual graphics processors, one graphics processor is typically used to render one frame whereas another graphics processor is used to render another frame. The graphics processors then output their frames alternately to a display controller which then displays the frames. This can greatly increase the performance capabilities of an image rendering system since the frame rendering is performed by a plurality of graphics processing devices. Such dual processing devices may also, instead of alternative frame rendering, may alternatively render a single line of a given frame. In any event, when the application requests that a full screen BLT operation be used, only one graphics processor in a multi-processor system is typically used at a time to do a full screen BLT. Accordingly, for full screen BLT operations, the second graphics processor may be unnecessarily idle although other rendering operations can be performed.
Accordingly, a need exists for a method and apparatus for improved storing data by image rendering processors.